1. Field of the Invention
The present invention generally relates to testing of integrated circuits and, more specifically, relates to a method and test circuit for testing memory write enable inputs.
2. Description of Related Art
Nadeau-Dostie et al. U.S. Pat. No. 4,969,148 granted on Nov. 6, 1990 for “Serial testing technique for embedded memories”, incorporated herein by reference, describes a testing circuit which interfaces serially with the data path of an embedded memory circuit formed from at least one memory unit having separated data input and output lines and tandem addressing. Part of the testing circuit is a series of two-input multiplexer units which are adapted to be embedded on the same chip as the memory circuit. The outputs of the multiplexer units connect to a respective one of the data input lines of the memory circuit. Except for the first bit position, a first input of each multiplexer unit connects to the data output line of the adjacent bit position in the memory circuit. The second input of the multiplexer units connects to the data bus of the chip. The testing circuit includes a finite state machine which connects to the first input of the multiplexer unit at the first bit position and to the data output line at the last bit position. During testing, the finite state machine actuates the multiplexer units to connect the first bits, and, for each address, outputs a series of test bits, shifts the bits through an addressed word by a series of read and write operations, and examines the bits after their passage through the addressed word for defects in the memory circuit at that address. The finite state machine may or may not be embedded on the same chip as the memory circuit.
Bit and byte write enables are commonly used in embedded memories. In addition, words may be arranged into groups of data bits having a different number of data bits than that of a byte. During execution of memory Built-In Self-Test (BIST) algorithms, these write enables are selectively connected to the memory global write enable and the test algorithm verifies that the write enables are not stuck inactive. During the execution of a scan or logic test, the write enables are typically tested for other faults, such as stuck active or shorted to other signals. The faults are tested up to the boundary of the memory itself. However, some of the same faults may originate from within the memory itself and, therefore, are not detected by test strategies heretofore employed.
There is a need for a method and a test circuit for detecting faults in bit and byte write enables that originate from within a memory.